01
Generate
Large candidate pools explore circuit topology, delays, thresholds, weights, and population structure.
Neuromorphic NPU hardware
Event-driven intelligence.
SYNA is building chips that compute with spikes, timing, and local learning.
ComputeSpikes + timing
LearningBounded STDP
First silicon130nm prototype
Next node28nm Vireon-1
L1Spike Core
L2Plasticity Engine
L3Reason Core
Vireon-1 / Neuromorphic Processing UnitSpike Routing Bus
GPUs move tensors.
SYNA moves events.
Validation
Evolved under pressure.
SYNA does not start with a fixed hand-designed circuit. Candidate programs are generated, simulated, attacked, and selected. Surviving patterns become hardware primitives for Vireon-1.
02
Stress
Every candidate is tested against timing, energy, logic, noise, and hardware failure modes.
03
Select
The survivors become the source material for the next generation and the hardware primitive library.
04
Vireon-1
Validated profiles map into the Vireon-1 stack: Spike Core, Plasticity Engine, and Reason Core.
300+
Programs evaluated across SYNA runs
5
Adversary classes per candidate
92.3
Best threshold-detection score
12
Generation where shadow inhibition emerged
Architecture
The three layers of Vireon-1.
Layer 1 detects events. Layer 2 adapts weights. Layer 3 wakes only when slower reasoning is needed.
Layer 01L1
Spike Core
Always-on event computation. Neuron populations fire only when input timing and threshold conditions justify activity.
Layer 02L2
Plasticity Engine
Bounded STDP updates adapt synaptic weights locally, without retraining the full system in the cloud.
Layer 03L3
Reason Core
A sleep-first control layer that wakes on high-confidence spike events and handles slower structured decisions.
Position
Built for temporal signals, not dense batches.
SYNA treats spike timing, configurable delay lines, local learning, and sparse activity as hardware primitives instead of software abstractions.
Conventional accelerators
- −Dense matrix multiplication as the center of compute.
- −High activity even when real-world signals are mostly idle.
- −Learning happens offline, then gets deployed as fixed weights.
- −Time is represented as data rather than used as hardware behavior.
SYNA direction
- +Spike timing and sparse events as the core representation.
- +Configurable delay lines for temporal computation.
- +On-chip plasticity for local adaptation.
- +Built for sensors, robotics, neural signals, and edge AI.
Roadmap
From primitive registry to silicon.
The path is deliberate: prove circuit behavior, translate it into hardware blocks, then fabricate a minimal test chip before scaling the architecture.
Now
Simulator + registry
Evaluate neuromorphic primitives: shadow inhibition, quorum voting, temporal gates, and adaptive thresholds.
Next
RTL / FPGA blocks
Translate useful primitives into spike routing, delay registers, weight memory, and output voting hardware.
V1
130nm test chip
Build a minimal prototype proving event routing, configurable delays, and low-power spike computation.
V2
28nm NPU
Scale density, power, and profile loading into a stronger neuromorphic processor for real edge workloads.
Contact
Help pressure-test Vireon-1.
SYNA is an early neuromorphic hardware project moving from evolved circuit behavior toward RTL, FPGA validation, and a first 130nm silicon prototype. The useful conversations are specific: what breaks, what is physically unrealistic, and what should be proven first.
Founder / CEO
Brandon Graff
Building Vireon-1 from evolved neuromorphic circuits toward RTL, FPGA validation, and first silicon.
Founder / CEO Contact